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FAN6753 -- Highly Integrated Green-Mode PWM Controller
February 2011
FAN6753 Highly Integrated Green-Mode PWM Controller
Features
High-Voltage Startup Low Operating Current: 2.7mA Adaptive Decreasing PWM Frequency to 22KHz Built-in Full-Range Frequency Hopping to Reduce EMI Emission Fixed PWM Frequency: 65KHz Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Synchronized Slope Compensation Internal Auto-Recovery Open-Loop Protection GATE Output Maximum Voltage Clamp: 18V VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP), Auto Recovery / Latch for Option Internal Auto-Recovery Sense Short-Circuit Protection for Option Constant Power Limit (Full AC Input Range) Internal OTP Sensor with Hysteresis Built-in 5ms Soft-Start Function Built-in LATCH Pin Pull HIGH (> 5.2V) Latch Function
Description
The highly integrated FAN6753 PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary adaptive green-mode function provides frequency modulation at light-load conditions. To avoid acousticnoise problems, the minimum PWM frequency is set above 22KHz. This green-mode function enables the power supply to meet international power conservation requirements. With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is also eliminated. To further reduce power consumption, FAN6753 is manufactured using the BiCMOS process, which allows an operating current of only 2.7mA. FAN6753 integrates a full-range frequency-hopping function internally that helps reduce EMI emission of a power supply with minimum line filters. Its built-in synchronized slope compensation achieves stable peakcurrent-mode control. The proprietary internal line compensation ensures constant output power limit over a wide AC input voltage range, from 90VAC to 264VAC. FAN6753 provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. PWM output is disabled until VDD drops below the UVLO lower limit, when the controller starts up again. As long as VDD exceeds ~26V, the internal OVP circuit is triggered. Available in the 8-pin SOP package.
Applications
General-purpose switch-mode power supplies and flyback power converters, including:

Power Adapters Open-Frame SMPS
Ordering Information
Part Number
FAN6753MY
Operating Temperature Range
-40C to +105C
Package
8-Lead, Small Outline Package
Packing Method
Tape & Reel
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
www.fairchildsemi.com
FAN6753 -- Highly Integrated Green-Mode PWM Controller
Marking Information
F: Fairchild Logo Z: Plant Code X: 1-Digit Year Code Y: 1-Digit Week Code TT: 2-Digit Die Run Code T: Package Type (M:SOP) P: Y=Green Package M: Manufacture Flow Code
Figure 1. Top Mark
ZXYTT 6753 TPM
Pin Configuration
LATCH FB SENSE GND
1 2 3 4
8 7 6 5
HV NC VDD GATE
Figure 2. Pin Configuration (Top View)
Pin Definitions
Pin #
1 2 3 4 5 6 7 8
Name
LATCH FB SENSE GND GATE VDD NC HV
Description
For external latch circuit used. When VLATCHth > 5.2V and after 100s, IC is latched off. 10K to GND is recommended. Internal has a sourcing current of 100A (ILATCH), 100A x10K. The voltage on this pin is 1V (under VLATCHth=5.2V). The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal on this pin and the current-sense signal on the SENSE pin. Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. Ground. The totem-pole output driver. Soft-driving waveform is implemented for improved EMI. Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the OVP trigger point. No connection. For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
www.fairchildsemi.com 2
FAN6753 -- Highly Integrated Green-Mode PWM Controller
Application Diagram
Figure 3. Typical Application
Internal Block Diagram
Figure 4. Functional Block Diagram
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
www.fairchildsemi.com 3
FAN6753 -- Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD VFB VSENSE VLATCH VHV PD JA TJ TSTG TL ESD DC Supply Voltage
(1, 2)
Parameter
FB Pin Input Voltage SENSE Pin Input Voltage LATCH Pin Input Voltage HV Pin Input Voltage Power Dissipation (TA50C) Thermal Resistance (Junction-to-Air) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Human Body Model, JEDEC:JESD22-A114 Charged Device Model, JEDEC:JESD22-C101
Min.
-0.3 -0.3 -0.3
Max.
30 7.0 7.0 7.0 500 400 141
Unit
V V V V V mW C/W C C C V
-40 -55
+125 +150 +260 5500 1500
Electrostatic Discharge Capability
Notes: 1. All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
www.fairchildsemi.com 4
FAN6753 -- Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD=15V and TA=25C unless otherwise noted.
Symbol
VDD Section VOP VDD-ON VDD-OFF IDD-ST IDD-OP IDD-OLP VTH-OLP VDD-OVP tD-VDDOVP HV Section IHV IHV-LC
Parameter
Continuously Operating Voltage Start Threshold Voltage Minimum Operating Voltage Startup Current Operating Supply Current Internal Sink Current IDD-OLP Off Voltage VDD Over-Voltage Protection VDD Over-Voltage Protection Debounce Time
Conditions
Min.
Typ.
Max. Units
22 V V V A mA A V V s
14.5 8.5 VDD-ON - 0.16V VDD=15V, GATE Open VTH-OLP+0.1V 30 6.5 25 75 VAC=90V (VDC=120V), VDD=0V HV=500V, VDD=VDD-OFF+1V
15.5 9.5 2.7 60 7.5 26 125
16.5 10.5 30 3.7 90 8.0 27 200
Supply Current Drawn from HV Pin Leakage Current after Startup
2.0
3.5 1
5.0 20
mA A
Oscillator Section Center Frequency fOSC Frequency in Nominal Mode Hopping Range tH-OP fOSC-G fDV fDT Hopping Period Green-Mode Frequency Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation VDD=11V to 22V TA=-20 to 85C 18 3.7 4.2 4.4 22 26 5 5 4.7 ms KHz % % 62 65 68 KHz
Continued on the following page... PWM Frequency fOSC
fOSC-G
VFB-G
VFB-N
VFB
Figure 5. VFB vs. PWM Frequency
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
www.fairchildsemi.com 5
FAN6753 -- Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
VDD=15V and TA=25C unless otherwise noted.
Symbol
LATCH Section VLATCHth tD-LATCH ILATCH AV ZFB VFB-OPEN VFB-OLP tD-OLP VFB-N VFB-G IFB-ZDC ZSENSE VSTHFL VSTHVA tPD tLEB tSS DCYMAX VGATE-L VGATE-H tr tf
Parameter
Conditions
VLATCHth > 5.2V, after 100s Latch Off VLATCH< VLATCHth
Min.
Typ.
Max. Units
Latch-Off Threshold Voltage Latch-Off De-bounce Time Output Current from LATCH Pin Input Voltage to Current-Sense Attenuation Input Impedance Output High Voltage FB Open-Loop Trigger Level Delay Time of FB Pin Open-Loop Protection Green-Mode Entry FB Voltage Green-Mode Ending FB Voltage Zero Duty-Cycle FB Current Input Impedance Current Limit Flatten Threshold Voltage Current Limit Valley Threshold Voltage Delay to Output Leading-Edge Blanking Time Period During Soft-Startup Time Maximum Duty Cycle Gate Low Voltage Gate High Voltage Gate Rising Time Gate Falling Time
5.0 40 92 1/4.5 4
5.3 100 100 1/4.0 5.3 4.8 56 3.0 2.4
5.6 160 108 1/3.5 7 5.6 5.0 62 3.2 2.6 1.5
V s A V/V k V V ms V V mA K
Feedback Input Section
FB Pin Open
5.0 4.6 50 2.8 2.2
Current-Sense Section 12 Duty>40% VSTHFL-VSTHVA Duty=0% 0.87 0.30 0.90 0.34 100 100 Startup Time 4.3 60 VDD=15V, IO=50mA VDD=12V, IO=50mA VDD=15V, CL=1nF VDD=15V, CL=1nF VDD=15V, GATE=6V VDD=22V +135 TOTP25 8 150 30 250 18 250 50 350 90 140 5.0 65 0.93 0.38 200 180 5.7 70 1.5
V V ns ns ms % V V ns ns mA V C C
GATE Section
IGATE-SOURCE Gate Source Current VGATE-CLAMP Gate Output Clamping Voltage Over-Temperature Protection Section (OTP) TOTP TRestart Protection Junction Temperature(3) Restart Junction Temperature(4)
Notes: 3. When activated, the output is disabled and the latch is turned off. 4. The threshold temperature for enabling the output again and resetting the latch, after over-temperature protection has been activated.
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
www.fairchildsemi.com 6
FAN6753 -- Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
25 5
20
4
IDD_ST (A)
15
IDD-OP (mA)
-30 -15 0 25 50 75 85 100 125
3
10
2
5
1
0 -40
0 -40
-30
-15
0
25
50
75
85
100
125
Temperature ()
Temperature ()
Figure 6. Startup Current (IDD-ST) vs. Temperature
18
Figure 7. Operation Supply Current (IDD-OP) vs. Temperature
12
17
11
VDD-ON (V)
VDD-OFF (V)
-30 -15 0 25 50 75 85 100 125
16
10
15
9
14
8
13 -40
7 -40 -30 -15 0 25 50 75 85 100 125
Temperature ()
Temperature ()
Figure 8. Start Threshold Voltage (VDD-ON) vs. Temperature
7 6
Figure 9. Minimum Operating Voltage (VDD-OFF) vs. Temperature
10
8 5 4 3 2 2 1 0 -40 0 -40
IHV-LC (A)
IHV (mA)
6
4
-30
-15
0
25
50
75
85
100
125
-30
-15
0
25
50
75
85
100
125
Temperature ()
Temperature ()
Figure 10. Supply Current Drawn from HV Pin (IHV) vs. Temperature
70
Figure 11. HV Pin Leakage Current After Startup (IHV-LC) vs. Temperature
72
68
70
66
DCYMAX (%)
-30 -15 0 25 50 75 85 100 125
FOSC (kHz)
68
64
66
62
64
60 -40
62 -40
-30
-15
0
25
50
75
85
100
125
Temperature ()
Temperature ()
Figure 12. Frequency in Normal Mode (fOSC) vs. Temperature
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
Figure 13. Maximum Duty Cycle (DCYMAX) vs. Temperature
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FAN6753 -- Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
7
62 60
6
58
VFB_OLP (V)
TLPS (ms)
56 54 52 50
5
4
3 -40 -30 -15 0 25 50 75 85 100 125
48 -40 -30 -15 0 25 50 75 85 100 125
Temperature ()
Temperature ()
Figure 14. FB Open-Loop Trigger Level (VFB-OLP) vs. Temperature
Figure 15. Delay Time of FB Pin Open-Loop Protection (tD-OLP) vs. Temperature
Figure 16. Output Current from LATCH Pin (ILATCH) vs. Temperature
28
Figure 17. Latch-Off Threshold Voltage (VLATCHth) vs. Temperature
27.5
VDD_OVP (V)
27
26.5
26
25.5
25 -40 -30 -15 0 25 50 75 85 100 125
Temperature ()
Figure 18. VDD Over-Voltage Protection (VDD-OVP) vs. Temperature
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
www.fairchildsemi.com 8
FAN6753 -- Highly Integrated Green-Mode PWM Controller
Functional Description
Startup Current
For startup, the HV pin is connected to the line input or bulk capacitor through an external diode and resistor, RHV, (1N4007 / 100K recommended). Typical startup current drawn from the HV pin is 3.5mA and charges the hold-up capacitor through the diode and resistor. When the VDD capacitor level reaches VDD-ON, the startup current switches off. At this moment, the VDD capacitor only supplies the FAN6753 before the auxiliary winding of the main transformer provides the operating current. For higher than 6KV surge test, RHV of 100K or above is recommended.
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the inrush current at startup. The built-in 5ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot.
Operating Current
Operating current is around 2.7mA. The low operating current enables better efficiency and reduces the requirement of VDD hold-up capacitance.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. FAN6753 inserts a synchronized, positive-going ramp at every switching cycle.
Green-Mode Operation
The proprietary green-mode function provides off-time modulation to reduce the switching frequency in lightload and no-load conditions. The on time is limited for better abnormal or brownout protection. VFB, which is derived from the voltage feedback loop, is taken as the reference. Once VFB is lower than the threshold voltage, the switching frequency is continuously decreased to the minimum green-mode frequency of around 22KHz.
Constant Output Power Limit
When the SENSE voltage across sense resistor RS reaches the threshold voltage, around 0.9V, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current proportional to tPD * VIN / LP. Since the delay is nearly constant regardless of the input voltage VIN, higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for a wide AC input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. The power limiter is designed as a positive ramp signal fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and VFB, the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP=(VFB-0.6)/4, the switch cycle is terminated immediately. VCOMP is internally clamped to a variable voltage around 0.9V for output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on spike occurs on the sense resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection is built in to prevent damage due to abnormal conditions. If the VDD voltage is over the over-voltage protection voltage (VDD-OVP) and lasts for tD-VDDOVP, the PWM pulses are disabled until the VDD voltage drops below the UVLO, then starts again. Overvoltage conditions are usually caused by open feedback loops.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at 15.5V and 9.5V, respectively. During startup, the holdup capacitor must be charged to 15.5V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 9.5V during startup. This UVLO hysteresis window ensures that the hold-up capacitor is adequate to supply VDD during startup.
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
External Latch Function (LATCH Pin)
The LATCH pin can be used to control the FAN6753 entering latch mode by pulling this pin over 5.2V for 100s. If floating, the LATCH pin is internally pulled HIGH to 3.5V. It is not recommended to float or short the LATCH pin to GND. This pin also includes a test mode to disable the jitter function. LATCH pin internally sources 100A, so place a resistor in series to GND. Do not let this voltage exceed 5.2V for the FAN6753 to function normally.
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FAN6753 -- Highly Integrated Green-Mode PWM Controller
Functional Description (Continued)
Limited Power Control
The feedback (FB) voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned off, VDD begins decreasing. When VDD goes below the turn-off threshold (~9.5V), the controller is totally shut down. VDD is charged up to the turn-on threshold voltage of 15.5V through the startup resistor until PWM output is restarted. This protection feature continues as long as the overloading condition persists.
Noise Immunity
Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FAN6753, and increasing the power MOS gate resistance also improve performance.
Over-Temperature Protection (Internal OTP)
The built-in temperature-sensing circuit shuts down PWM output once the junction temperature exceeds 135C. While PWM output is shut down, VDD gradually drops to the UVLO voltage (around 7.5V). Then VDD charges up to the startup threshold voltage of 15.5V through the startup resistor until PWM output is restarted. This "hiccup" mode protection occurs repeatedly as long as the temperature remains above 130C. The temperature hysteresis window for the OTP circuit is 25C.
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
www.fairchildsemi.com 10
FAN6753 -- Highly Integrated Green-Mode PWM Controller
Physical Dimensions
5.00 4.80 3.81
8 5
A
0.65
B
6.20 5.80
4.00 3.80
1 4
1.75
5.60
PIN ONE INDICATOR
(0.33)
1.27
0.25
M
CBA
1.27
LAND PATTERN RECOMMENDATION
0.25 0.10 1.75 MAX
C 0.10 0.51 0.33 0.50 x 45 0.25 C
SEE DETAIL A
0.25 0.19
OPTION A - BEVEL EDGE
R0.10 R0.10
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13
8 0 0.90 0.406
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 19. 8-Pin Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
www.fairchildsemi.com 11
FAN6753 -- Highly Integrated Green-Mode PWM Controller
(c) 2009 Fairchild Semiconductor Corporation FAN6753 * Rev. 1.0.3
www.fairchildsemi.com 12

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